(1) Field of the Invention
The invention relates to burn-in of integrated circuit devices, and, more particularly, to a circuit and a method for wafer level burn-in of a memory device.
(2) Description of the Prior Art
Burn-in is a frequently used technique in the art of integrated circuit manufacturing. A product burn-in is performed to improve product reliability. Burn-in techniques typically involve circuit stressing using extended voltage ranges and/or temperatures. By stressing the circuit, defects, such as poor oxide quality or borderline hot carrier capability, will be exposed while the product is still in the factory. Burn-in failures will reduce the product yield within the factory. However, customer satisfaction is improved by the increased reliability of the shipped product.
Burn-in is typically performed after product packaging but before the final packaged test. This provides an excellent burn-in performance and detects any problems due to the packaging process. However, many manufactures now sell product at the wafer level. Further, these wafer level products have stringent reliability requirements from customers. For example, a memory circuit may have a known good die (KGD) requirement of less than or equal to 200 defects/million after packaging. Due to random defect effects, it is not feasible to insure such quality levels without stressing the circuits. Therefore, to meet this quality requirement at the wafer level, circuit manufacturer must implement a wafer level, circuit stressing method.
Where manufacturers have implemented wafer level burn-in, these methods have several problems. First,-the prior art, wafer level burn-in methods typically require probing all of the pads on the circuit die. This leads to two issues. First, probing the circuit pads can adversely affect subsequent wire bonding. The burn-in process represents an additional test probe of each pad and, therefore, causes a reduced overall bondability. Second, the burn-in test system has a limited number of input and output (I/O) channels. If all of the die pads must be probed, then only a few devices can be burned in simultaneously. This limits manufacturing throughput or requires a large investment in equipment.
Another problem with the prior art, burn-in methods is the lack of a comprehensive stress regime. For example, in the art of static RAM (SRAM) devices, two types of reliability issues must be addressed during burn-in: gate oxide reliability and hot carrier reliability. It is found that gate oxide defects are best detected using a static burn-in technique where a large voltage is supported across the gate oxide structure over a significant time. It is also found that the hot carrier defects are best detected using dynamic burn-in methods where short channel devices are frequently switched in the presence of the large supply voltage. The prior art, burn-in methods do not adequately combine these approaches to comprehensively stress devices at the wafer level.
Several prior art inventions relate to methods and circuits for device burn-in. U.S. Pat. No. 6,233,184 to Barth et al discloses a wafer burn-in method and device. This method uses a BIST circuit on the circuit die to exercise a memory array during burn-in conditions. U.S. Pat. No. 6,255,836 to Schwarz et al describes a memory device having a BIST unit. The BIST unit is re-configurable to a test mode for stressing the memory array.
A principal object of the present invention is to provide an effective and very manufacturable circuit to burn-in a circuit at the wafer level.
A further object of the present invention is to provide a wafer level, burn-in circuit that uses a minimal number of reserved I/O pads.
A yet further object of the present invention is to provide a wafer level, burn-in circuit that provides dynamic and static burn-in stress to a memory circuit.
A further object of the present invention is to provide a method to burn-in a circuit at the wafer level.
A yet further object of the present invention is to provide a method to combine dynamic and static burn-in stress on a memory circuit.
In accordance with the objects of this invention, a memory device with burn-in capability is achieved. The device comprises an array of memory cells and a burn-in test block. The burn-in test block comprises a memory address generator, a data pattern generator, and a command pattern generator. The burn-in test block is capable of writing data to the memory cells, of turning ON all word lines in the array, and of holding the array in a static mode.
Also in accordance with the objects of this invention, a method of performing wafer level burn-in of a memory device is achieved. The method comprises, first, providing a memory device on a wafer. The memory device comprises an array of memory cells and a burn-in test block. The burn-in test block comprises a memory address generator, a data pattern generator, and a command pattern generator. The burn-in test block is capable of writing data to the memory cells, of turning ON all word lines in the array, and of holding the array in a static mode. Second, inputs of to the burn-in test block on the memory device are probed. Third, the memory device is dynamically burned in by writing to the memory cells using the burn-in test block. Finally, the memory device is statically burned-in by writing to the memory cells, by turning ON all the word lines, and by holding the array in the static mode using the burn-in test block. The method is extendable to the simultaneous burn-in of a plurality of such memory devices on a wafer.